Electronic packaging and specifically integrated circuit packaging and the interconnection between such devices have become a significant performance limiting elements of electronic circuits. Presently, semiconductors operate at internal clock speeds that surpass the current electronic interconnection infrastructure's ability to carry signals between semiconductors.
Copper (and other conductive metal) interconnect elements, including but not limited to semiconductor substrates (packages), connectors, and printed circuit boards have not followed the historical curve of semiconductor speed improvement; although arguably it has not been until recently that the copper interconnect represented a significant performance barrier in chip-to-chip systems. A well designed interconnection channel would allow two or more IC chips in close proximity to one another to communicate at their native speeds, as if they were a single chip.
Copper is in fact capable of transmitting signals at near the speed of light in a vacuum or air. However, in practice electrical circuits cannot be practically established in vacuums, and are typically composed of several components that must connect at points of potential discontinuity. The electrical circuits must be held in place physically by structures made of an insulating material, which normally impedes the signal propagation.
Copper interconnect systems typically incorporate several sources of signal discontinuity and disturbance, which degrade signal integrity and reduce speed. These include variances in metal conductor path height, width, length, and materials, proximity to other circuit paths, through-hole vias, connector and solder joints, and capacitive stubs.
One fundamental design objective for high speed circuits is to incorporate the shortest signal path between two objects, which geometry teaches is a straight line. Typically the signal path from chip-to-chip in an electronic system travels from the semiconductor, through the package, into the circuit board, through another package and to the second semiconductor. This approach involves a relatively tortuous circuit route that does not closely track the straight line design objective. However, by routing some or all signals through structures that create signal paths that do not traverse the package or the printed circuit board, a more straight line path can be accomplished. A path that avoids the printed circuit board and the package may also avoid common elements of those structures, such as vias and stubs, as well as other signal disruptors.
New interconnect elements may facilitate the creation of a more direct path for some or all signals. Structures that establish an electrical path directly from one chip to another chip may create performance advantages.
It is believed that such innovations and future products based on them will meet or exceed all cost and performance design requirements with minimal disruption to the manufacturing infrastructure. At the same time, it will remove most current roadblocks to high speed signal transmission from chip to chip.